In conventional semiconductor memories, as common subject to integrated circuits, the wider the scale of semiconductor memories, the higher the rate of the defect occurs, the longer time required for testing is, or the larger the tester for the memories. Therefore, it is necessary to provide a test method and additional test circuits capable of efficiently in a short time. Moreover, it is important to develop a test method with a small scale of the additional circuits to be small and a recover method in which a recovery of the detected defect can be performed with ease and a few resources.
As a result, it is important to satisfy the following requirements in order to realize a mass semiconductor memory:    (1) a construction for an easy test;    (2) a high rate and simple test method; and    (3) a small additional test circuit, and a recover with a few resources.
Conventional test method of semiconductor memories is performed in such a manner that random data are supplied from outside and testing is carried out by all the combinations thereof, however, a large tester and a long test time are required to supply all patterns from outside, read and write the patterns from outside, and analyze the results thereof.
Current major test methods for mass semiconductor memories are as follows:    (a) a simple static test method, and    (b) a close dynamic test method.By combining these methods, firstly, (a) as an initial simple sort method, recoverable memories are recovered by the evaluation of the test results detecting malfunctions by “reading ‘0’ incorrectly in spite of writing ‘1’ statically” or “reading ‘1’ incorrectly in spite of writing ‘0’ statically”; secondary, (b) memories determined as good in the initial test and recovery are exhaustively tested and sorted, and recoverable memories are recovered. As a result, all memories are tested and sorted.
Thus, current mass semiconductor memories usually incorporate the additional test circuits necessary for simple and minimum test. This is referred as “built-in self-test” in general, and this technique is disclosed in U.S. Pat. No. 5,999,464: “SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CHECKING SAME FOR DEFECT”, for example.
In the above-mentioned simple test for initially sorting semiconductor memories, the necessary condition is a set of:    (i) a construction for an easy test, and    (ii) a simple test method.Generally, in the construction for easy test in the semiconductor memory, there are a normal mode in which the memory operates as a normal memory and a test mode in which the memory is tested, the test mode also has a basic self-test and a test from outside. In any cases, in order to perform the quick and precise test of the memory, it is necessary to provide a test circuit suitable for these tests or an additional test circuit in aid of the test on the integrated circuit. In addition, the self-test has an advantageous feature in that the test can be performed distributedly and independently of one another in an integrated circuit in a short time, and a plurality of semiconductor memories can be tested distributedly in parallel.
Generally, in testing of the fault in the memory, there are a sequential method and a batch method. In the sequential method, data and addresses are supplied from outside or are self-generated inside for testing every operation in the integrated circuit, and the faults accompanying write and read operations are detected. For a simple test performed mainly in the integrated circuit, if a defect or a fault is detected in the test, the test is stopped at the location where the detect or the fault is detected, and the selected path of the address or the data where the defect or the fault is detected is informed, whereas, if no defect or the fault is detected in the data, a next address is set and a series of test is repeated. In the batch method, all the test data are written at one time, after then, all of them are read, and all of the locations where the defects or the faults are detected are collected and processed, so that the address or selection path are recovered in a unit.
A conventional method of recovering the defect of the semiconductor memory is performed in such a manner that the defect location, an address containing the location, or a selection path of the data is cut off by a fuse, an electronic means, or a mechanical means, and is diverted to a location prepared as a reserve. Other examples of the method include:    an electrical cut-off by an EEPROM, a PROM, or a flash memory; and    an cut-off by a laser beam machining.
In a conventional construction considering the defect recovery of the semiconductor memory, also, in order to recover the memory optimally with the above-mentioned recovery method, various attempts are made in switching of defect locations and arrangements, and after defect locations are cut off, reserved locations are connected thereto. As an example of the method of switching connection with the use of circuits, there is a method in which an address is assigned over two addresses or a data line is wired over the selection path of two data lines, and if a defect is detected, switching is carried out from that location as a boundary to shift to the next, for example, as described in M. Yamada, etc: “A system LSI memory redundancy technique using, an ie-Flash (inverse-gate-electrode flash) programming circuit”, Symp. On VLSI Circuits, pp. 71–72. June 2001.
Generally, in the integrated circuit, if a signal is taken outside, the power consumption increases and operating rate decreases in comparison with internal processing thereof, a loss increases of the power consumption from several times to several tens of times; thus, it is prefer to perform the internal process if possible. In testing, similarly, in the test method for sorting semiconductor memories at first, a simple and effective test method with built-in test circuits is widely used. For this reason, a little addition of incorporated test circuits is negligible for the mass memory.
In addition, a conventional semiconductor memory is manufactured in such a way that the written data are read as the written values. However, U.S. Pat. No. 6,205,047: “DATA MEMORY DEVICE HAVING AN EXCLUSIVE-OR FUNCTION AND METHOD OF READING DATA THEREFROM” proposes a method of performing an exclusive-OR operation to read the stored content by reading the stored content positively or negatively with the control by retrieval data for retrieving identity, and thus, it is possible to detect a mismatch between the stored content and the test data when they do not match to each other.
Nevertheless, current major methods of testing faults use a round robin method in which a test pattern capable of detecting all faults is compared with the result obtained by storing and reading the test pattern. These methods require O(N2) times of tests where the number of memory elements is N, that is, tests are required over an exponential number of times, and thus, a subject in the mass memory is how read and write tests of all these combinations should be performed in a short time or in a few number of times of tests.
Therefore, the test items for sorting the product of the memory at first is limited to a stuck-at-1 fault, by which the variant of a logic function is always fixed to 1, or a stuck-at-0 fault, by which it is fixed to 0.
The test is performed by a method of testing the semiconductor memory at a high speed by providing an additional test circuit in the memory, and by a method of testing the memory in a short time or at a small number of times of comparison.
It should be noted that the precise test is not performed in the present invention, however, the semiconductor memory that incorporates minimum additional circuits according to the present invention may be tested by cooperating with an external tester and comparing the memory with the specification thereof, as required.